Reducing Capacity and Conflict Misses using Set Saturation Levels Dyer Rol´an, Basilio B. Fraguela and Ram´on Doallo Grupo de Arquitectura de Computadores Departamento de Electr´onica e Sistemas Universidade da Coru˜

Source URL: www.des.udc.es

• Cache
• Central processing unit
• Computer architecture
• Computer memory
• CPU cache
• Virtual memory
• Cache algorithms
• Thrashing
• DSBC
• Memory hierarchy
• Microarchitecture
• Draft:Cache memory

Predicting Memory-Access Cost Based on Data-Access Patterns Surendra Byna Xian-He Sun Illinois Institute of Technology {renbyna, sun}@iit.edu Abstract

Source URL: wgropp.cs.illinois.edu

• Cache
• Computer memory
• Computer architecture
• Central processing unit
• Virtual memory
• CPU cache
• Locality of reference
• Loop interchange
• Memory hierarchy
• Loop nest optimization
• Thrashing
• Page table

Applying Amdahl’s Other Law to the data center D. Cohen

Source URL: www.mulix.org

• Computer architecture
• Computer memory
• Hypervisor
• I/O virtualization
• Cache
• Virtualization
• Storage area network
• CPU cache
• Hyper-V
• Memory hierarchy
• Logical partition
• Direct memory access

S CIEntIfIC ProgrAmmIng Editors: Konstantin Läufer,

Source URL: www.blosc.org

• Computing
• Computer memory
• Computer architecture
• Computer engineering
• Computer hardware
• Cache
• Parallel computing
• Central processing unit
• CPU cache
• Memory hierarchy
• Multi-core processor
• Locality of reference

Ehcache 2.6.x Documentation Documentation Overview............................................................................................................................1/321 Ehcache {$ehcache_documentation_version

Source URL: www.ehcache.org

• Cache
• Computer architecture
• Terracotta
• Inc.
• Ehcache
• Distributed cache
• Web cache
• Memory hierarchy

Object-oriented Packet Caching for ICN Yannis Thomas George Xylomenos

Source URL: conferences2.sigcomm.org

• Cache
• Computer memory
• Computer architecture
• Computing
• Computer engineering
• Computer hardware
• CPU cache
• Cache hierarchy

Location-Aware Cache Management for Many-Core Processors with Deep Cache Hierarchy Jongsoo Park1 , Richard M. Yoo1 , Daya S. Khudia2 , Christopher J. Hughes1 , and Daehyun Kim1 1 Parallel Computing Lab, Intel Corporatio

Source URL: pcl.intel-research.net

Optimizing Communication and Capacity in a 3D Stacked Reconfigurable Cache Hierarchy ∗ Niti Madan† , Li Zhao‡ , Naveen Muralimanohar† , Aniruddha Udipi† , Rajeev Balasubramonian† , Ravishankar Iyer‡ , Sriha

Source URL: www.cs.utah.edu

Improving Data Access Efficiency by Using a Tagless Access Buffer (TAB) Alen Bardizbanyan Chalmers University of Technology

Source URL: www.cs.fsu.edu

• Central processing unit
• Computer architecture
• Whitespace
• CPU cache
• Cache
• Tab key
• C
• Memory hierarchy
• Translation lookaside buffer
• Computer memory
• Computing
• Computer hardware